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19-2878; Rev 0; 7/03
2:1 Multiplexers and 1:2 Demultiplexers with Loopback
General Description
The MAX9394/MAX9395 consist of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. The multiplexer section (channel B) accepts two low-voltage differential signaling (LVDS) inputs and generates a single LVDS output. The demultiplexer section (channel A) accepts a single LVDS input and generates two parallel LVDS outputs. The MAX9394/MAX9395 feature a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A. Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELA and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the commonmode voltage exceeds the specified range. The MAX9394 provides high-level input fail-safe detection for HSTL, LVDS, and other GND-referenced differential inputs. The MAX9395 provides low-level fail-safe detection for CML, LVPECL, and other VCC-referenced differential inputs. Ultra low 91psP-P (max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in highspeed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.5GHz operation and less than 87ps (max) skew between channels. LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS outputs drive 100 loads. The MAX9394/MAX9395 are offered in 32pin TQFP and 28-pin thin QFN packages and operate over the extended temperature range (-40C to +85C).
Features
o Guaranteed 1.5GHz Operation with 250mV Differential Output Swing o Simultaneous Loopback Control o 2ps(RMS) (max) Random Jitter o AC Specifications Guaranteed for 150mV Differential Input o Signal Inputs Accept Any Differential Signaling Standard o LVDS Outputs for Clock or High-Speed Data o High-Level Input Fail-Safe Detection (MAX9394) o Low-Level Input Fail-Safe Detection (MAX9395) o +3.0V to +3.6V Supply Voltage Range o LVCMOS/LVTTL Logic Inputs
MAX9394/MAX9395
Ordering Information
PART MAX9394EHJ MAX9394ETI* MAX9395EHJ MAX9395ETI* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP 28 Thin QFN 32 TQFP 28 Thin QFN
*Future product--contact factory for availability.
Typical Operating Circuit
+3.0V TO +3.6V 0.1F 0.01F VCC Z0 = 50 100 Z0 = 50 INA INA OUTA0 Z0 = 50 100
MAX9394 MAX9395
OUTA0
Z0 = 50
Applications
High-Speed Telecom/Datacom Equipment Central Office Backplane Clock Distribution DSLAM Protection Switching Fault-Tolerant Systems
LVCMOS/LVTTL LOGIC INPUTS
INB0 INB0 INB1 INB1 ENA0 ENA1 ENB
OUTA1
Z0 = 50
LVDS RECEIVER
OUTA1
Z0 = 50
OUTB
Z0 = 50
OUTB
Z0 = 50
LB_SELA LB_SELB BSEL GND GND GND GND
Pin Configurations and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, _SEL, LB_SEL_ to GND........................................................-0.3V to (VCC + 0.3V) IN_ _ to IN_ _..........................................................................3V Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous Continuous Power Dissipation (TA = +70C) 32-Pin TQFP (derate 13.1mW/C above +70C)........1047mW 28-Pin 5mm x 5mm Thin QFN (derate 20.8mW/C above +70C) .............................1667mW Junction-to-Ambient Thermal Resistance in Still Air 32-Pin TQFP............................................................+76.4C/W 28-Pin 5mm x 5mm Thin QFN....................................+48C/W Junction-to-Case Thermal Resistance 28-Pin 5mm x 5mm Thin QFN......................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection (Human Body Model) (IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, SEL_, LB_SEL_) ..2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, EN_ _ = VCC, VCM = +0.05V to (VCC - 0.6V) (MAX9394), VCM = +0.06V to (VCC - 0.05V) (MAX9395), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25C.) (Notes 1, 2, and 3)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current DIFFERENTIAL INPUTS (IN_ _, IN_ _) Differential Input Voltage VID VCM MAX9395 Input Current LVDS OUTPUTS (OUT_ _, OUT_ _) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Common-Mode Voltage Change in Magnitude of VOS Between Complementary Output States VOD VOD VOS VOS RL = 100, Figure 2 Figure 2 Figure 2 Figure 2 1.125 250 350 1.0 1.25 1.0 450 50 1.375 50 mV mV V mV IIN_ _, IIN_ _ MAX9394 MAX9395 |VID| < 3.0V |VID| < 3.0V 0.6 -75 -10 VILD > 0V and VIHD < VCC, Figure 1 MAX9394 Input Common-Mode Range 0.1 0.05 3.0 VCC 0.6 VCC 0.05 10 100 V SYMBOL VIH VIL IIH IIL VIN = +2.0V to VCC VIN = 0V to +0.8V CONDITIONS MIN 2.0 0 0 0 TYP MAX VCC 0.8 20 10 UNITS V V A A
LVCMOS/LVTTL INPUTS (EN_ _, BSEL, LB_SEL_)
V
A
2
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2:1 Multiplexers and 1:2 Demultiplexers with Loopback
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, EN_ _ = VCC, VCM = +0.05V to (VCC - 0.6V) (MAX9394), VCM = +0.06V to (VCC - 0.05V) (MAX9395), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25C.) (Notes 1, 2, and 3)
PARAMETER Output Short-Circuit Current (Output(s) Shorted to GND) Output Short-Circuit Current (Outputs Shorted Together) SUPPLY CURRENT RL = 100, EN_ _ = VCC Supply Current ICC RL = 100, EN_ _ = VCC, switching at 670MHz (1.34Gbps) 53 53 65 65 mA SYMBOL VID = 100mV (Note 4) CONDITIONS VOUT_ _ or V OUT_ _ = 0V VOUT_ _ = V OUT_ _ = 0V MIN TYP 30 17 5 MAX 40 mA 24 12 mA UNITS
MAX9394/MAX9395
|IOS|
|IOSB|
VID = 100mV, VOUT_ _ = V OUT_ _ (Note 4)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, fIN < 1.34GHz, tR_IN = tF_IN = 125ps, RL = 100 1%, |VID| 150mV, VCM = +0.075V to (VCC - 0.6V) (MAX9394 only), VCM = +0.6V to (VCC - 0.075V) (MAX9395 only), EN_ _ = VCC, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, fIN = 1.34GHz, TA = +25C.) (Note 5)
PARAMETER SEL to Switched Output Disable Time to Differential Output Low Enable Time to Differential Output High Switching Frequency Low-to-High Propagation Delay High-to-Low Propagation Delay Pulse Skew |tPLH - tPHL| Output Channel-to-Channel Skew Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (80% to 20%) Added Random Jitter Added Deterministic Jitter SYMBOL tSWITCH tPHD tPDH fMAX tPLH tPHL tSKEW tCCS tR tF tRJ tDJ Figure 3 Figure 4 Figure 4 VOD > 250mV Figures 1, 5 Figures 1, 5 Figures 1, 5 (Note 6) Figure 6 (Note 7) fIN_ _ = 100MHz, Figures 1, 5 fIN_ _ = 100MHz, Figures 1, 5 fIN_ _ = 1.34GHz, clock pattern (Note 8) 1.34Gbps, 2 - 1 PRBS (Note 8)
23
CONDITIONS
MIN
TYP
MAX 1.1 1.7 1.7
UNITS ns ns ns GHz
1.5 340 340
2.2 567 562 12.4 16 720 720 86 87 187 187 2 60 91
ps ps ps ps ps ps ps(RMS) psP-P
112 112
154 152
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except VID, VOD, and VOD. Current into the device defined as positive. Current out of the device defined as negative. DC parameters production tested at TA = +25C and guaranteed by design and characterization for TA = -40C to +85C. Current through either output. Guaranteed by design and characterization. Limits set at 6 sigma. tSKEW is the magnitude difference of differential propagation delays for the same output over the same condtions. tSKEW = |tPHL - tPLH|. Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition under the same conditions. Does not apply to loopback mode. Note 8: Device jitter added to the differential input signal. _______________________________________________________________________________________ 3
2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
Typical Operating Characteristics
(VCC = +3.3V, |VID| = 0.2V, VCM = +1.2V, TA = +25C, fIN = 1.34GHz, Figure 5.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9394/95 toc01
OUTPUT AMPLITUDE vs. FREQUENCY
MAX9394/95 toc02
OUTPUT RISE/FALL TIME vs. TEMPERATURE
fIN = 100MHz
MAX9394/95 toc03
70 65 SUPPLY CURRENT (mA) 60 55 50 45 40 35 30 -40 -15 10 35 60 VCC = +3.3V VCC = +3.0V VCC = +3.6V
400 350 OUTPUT AMPLITUDE (mV) 300 250 200 150 100 50 0
180 170 RISE/FALL TIME (ps) 160 150 140 130 120
tR tF
85
0
0.4
0.8
1.2
1.6
2.0
2.4
-40
-15
10
35
60
85
TEMPERATURE (C)
FREQUENCY (GHz)
TEMPERATURE (C)
PROPAGATION DELAY vs. TEMPERATURE
MAX9394/95 toc04
MAX9394 DIFFERENTIAL INPUT CURRENT vs. TEMPERATURE
10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50
MAX9394/95 toc05
MAX9395 DIFFERENTIAL INPUT CURRENT vs. TEMPERATURE
VIN_ _ = VCC 70 INPUT CURRENT (A) 60 50 40 30 20 10 0 VIN_ _ = (VCC - 3.0V) -40 -15 10 35 60 85 VIN_ _ = (VCC - 0.1V)
MAX9394/95 toc06
600 590 PROPAGATION DELAY (ps) 580 570 560 550 540 530 520 510 500 -40 -15 10 35 60
VIN_ _ = 0V VIN_ _ = 3.0V
80
INPUT CURRENT (A)
VIN_ _ = 0.1V
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
MAX9394 DIFFERENTIAL INPUT CURRENT vs. VIHD
MAX9394/95 toc07
MAX9395 DIFFERENTIAL INPUT CURRENT vs. VILD
70 60 INPUT CURRENT (A) 50 40 30 20 10 0 -10 VCC = +3V VCC = +3.6V IN_ _ OR IN_ _ = VCC
MAX9394/95 toc08
5 0 -5 INPUT CURRENT (A) -10 -15 -20 -25 -30 -35 -40 0 0.6 1.2 1.8 VIHD (V) 2.4 3.0 VCC = +3.6V VCC = +3V IN_ _ OR IN_ _ = GND
80
3.6
0
0.6
1.2
1.8 VILD (V)
2.4
3.0
3.6
4
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2:1 Multiplexers and 1:2 Demultiplexers with Loopback
Pin Description
PIN TQFP 1, 2, 3, 30, 31, 32 4, 9, 20, 25 5 6 7 QFN 1, 2, 28 3, 8, 18, 23 4 5 6 NAME N.C. GND ENB OUTB OUTB FUNCTION No Connection. Not internally connected. Ground Channel B Output Enable. Drive ENB high to enable the LVDS outputs for channel B. An internal 435k resistor to GND pulls ENB low when unconnected. Channel B LVDS Noninverting Output. Connect a 100 termination resistor between OUTB and OUTB at the receiver inputs to ensure proper operation. Channel B LVDS Inverting Output. Connect a 100 termination resistor between OUTB and OUTB at the receiver inputs to ensure proper operation. Power-Supply Input. Bypass each VCC to GND with a 0.1F and 0.01F ceramic capacitor. Install both bypass capacitors as close to the device as possible, with the 0.01F capacitor closest to the device. LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal 128k pullup resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68k resistor to GND pulls the input low when unconnected (MAX9395). LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal 128k pullup resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68k resistor to GND pulls the input low when unconnected (MAX9395). Loopback Select for Channel B Output. Connect LB_SELB to GND or leave unconnected to reproduce the INB_ (INB_) differential inputs at OUTB (OUTB). Connect LB_SELB to VCC to loop back the INA (INA) differential inputs to OUTB (OUTB). An internal 435k resistor to GND pulls LB_SELB low when unconnected. LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal 128k pullup resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68k resistor to GND pulls the input low when unconnected (MAX9395). LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal 128k pullup resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68k resistor to GND pulls the input low when unconnected (MAX9395). Channel B Multiplexer Control Input. Selects the differential input to reproduce at the B channel differential output. Connect BSEL to GND or leave unconnected to select the INB0 (INB0) set of inputs. Connect BSEL to VCC to select the INB1 (INB1) set of inputs. An internal 435k resistor to GND pulls BSEL low when unconnected. Channel A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435k resistor to GND pulls the ENA1 low when unconnected. Channel A1 LVDS Inverting Output. Connect a 100 termination resistor between OUTA1 and OUTA1 at the receiver inputs to ensure proper operation. Channel A1 LVDS Noninverting Output. Connect a 100 termination resistor between OUTA1 and OUTA1 at the receiver inputs to ensure proper operation.
MAX9394/MAX9395
8, 13, 24, 29
7, 22, 27
VCC
10
9
INB0
11
10
INB0
12
11
LB_SELB
14
12
INB1
15
13
INB1
16
14
BSEL
17 18 19
15 16 17
ENA1 OUTA1 OUTA1
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5
2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
Pin Description (continued)
PIN TQFP 21 22 23 QFN 19 20 21 NAME ENA0 OUTA0 OUTA0 FUNCTION Channel A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An internal 435k resistor to GND pulls ENA0 low when unconnected. Channel A0 LVDS Inverting Output. Connect a 100 termination resistor between OUTA0 and OUTA0 at the receiver inputs to ensure proper operation. Channel A0 LVDS Noninverting Output. Connect a 100 termination resistor between OUTA0 and OUTA0 at the receiver inputs to ensure proper operation. LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Noninverting Input. An internal 128k pullup resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68k resistor to GND pulls the input low when unconnected (MAX9395). LVDS/HSTL (MAX9394) or LVPECL/CML (MAX9395) Inverting Input. An internal 128k pullup resistor to VCC pulls the input high when unconnected (MAX9394). An internal 68k resistor to GND pulls the input low when unconnected (MAX9395). Loopback Select for Channel A Output. Connect LB_SELA to GND or leave unconnected to reproduce the INA (INA) differential inputs at OUTA_ (OUTA_). Connect LB_SELA to VCC to loop back the INB_ (INB_) differential inputs to OUTA_ (OUTA_). An internal 435k resistor to GND pulls LB_SELA low when unconnected. Exposed Paddle. Connect to GND for optimal thermal and EMI characteristics.
26
24
INA
27
25
INA
28
26
LB_SELA
--
--
EP
Detailed Description
The LVDS interface standard provides a signaling method for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 standard. LVDS utilizes a lower voltage swing than other communication standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9394/MAX9395 high-speed, low-power 2:1 multiplexers and 1:2 demultiplexers with loopback provide signal redundancy switching in telecom and storage applications. These devices select one of two remote signal sources for local input and buffer a single local output signal to two remote receivers. The multiplexer section (channel B) accepts two differential inputs and generates a single LVDS output. The demultiplexer section (channel A) accepts a single differential input and generates two parallel LVDS outputs. The MAX9394/MAX9395 feature a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A. LB_SELA and LB_SELB provide independent loopback control for each channel.
6
Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELA and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility.
Input Fail-Safe
The differential inputs of the MAX9394/MAX9395 possess internal fail-safe protection. Fail-safe circuitry forces the outputs to a differential-low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9394 provides high-level input fail-safe detection for LVDS, HSTL, and other GND-referenced differential inputs. The MAX9395 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs.
Select Function
BSEL selects the differential input pair to transmit through OUTB (OUTB) for LB_SELB = GND or through OUTA_ (OUTA_) for LB_SELA = VCC. LB_SEL_ controls the loopback function for each channel. Connect LB_SEL_ to GND to select the normal inputs for each channel. Connect LB_SEL_ to VCC to enable the loop-
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2:1 Multiplexers and 1:2 Demultiplexers with Loopback
back function. The loopback function routes the input of channel A to the output of channel B, and the inputs of channel B to the outputs of channel A. See Tables 1 and 2 for a summary of the input/output routing between channels.
MAX9394/MAX9395
VIN_ _ VID = 0V VIN_ _ tPLH VOUT_ _ VOD = 0V VOUT_ _ VOD = 0V tPHL VID = 0V
VIHD
VILD
Enable Function
The EN_ _ logic inputs enable and disable each set of differential outputs. Connect EN_ 0 to VCC to enable the OUT_0/OUT_0 differential output pair. Connect EN_0 to GND to disable the OUT_0/OUT_0 differential output pair. The differential output pairs assert to a differential low condition when disabled.
Applications Information
Differential Inputs
The MAX9394/MAX9395 inputs accept any differential signaling standard within the specified common-mode voltage range. The fail-safe feature detects commonmode input signal levels and generates a differential output low condition for undriven inputs or when the common-mode voltage exceeds the specified range (VCM VCC - 0.6V, MAX9394; VCM 0.6V, MAX9395). Leave unused inputs unconnected or connect to VCC for the MAX9394 or to GND for the MAX9395.
50% 20% tR
80% VOD = 0V
80% 50% VOD = 0V 20% tF
VID = VIN_ _ - VIN_ _ VOD = VOUT_ _ - VOUT_ _
Figure 1. Output Transition Time and Propagation Delay Timing Diagram
Power-Supply Bypassing
Bypass each VCC to GND with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible. Install the 0.01F capacitor closest to the device.
OUT_ _ MAX9394/MAX9395 RL/2 IN_ _ VOS IN_ _ RL/2 EN_ _ = HIGH VID = VIN_ _ - VIN_ _
VOD
Differential Traces
Input and output trace characteristics affect the performance of the MAX9394/MAX9395. Connect each input and output to a 50 characteristic impedance trace. Maintain the distance between differential traces and eliminate sharp corners to avoid discontinuities in differential impedance and maximize common-mode noise immunity. Minimize the number of vias on the differential input and output traces to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces.
OUT_ _
VOD = VOD - VOD* RL = 100 1% VOS = VOS - VOS* VOD AND VOS ARE MEASURED WITH VID = +100mV. VOD* AND VOS* ARE MEASURED WITH VID = -100mV.
Output Termination
Terminate LVDS outputs with a 100 resistor between the differential outputs at the receiver inputs. LVDS outputs require 100 termination for proper operation. Ensure that the output currents do not exceed the current limits specified in the Absolute Maximum Ratings. Observe the total thermal limits of the MAX9394/ MAX9395 under all operating conditions.
Figure 2. Test Circuit for VOD and VOS
Cables and Connectors
Use matched differential impedance for transmission media. Use cables and connectors with matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables.
7
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2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
INB0 VID = 0V INB0 INB1 VID = 0V INB1 VIHD VILD VIHD VILD
VIH 1.5V BSEL OUT_ _ INB0 OUT_ _ tSWITCH EN_0 = EN_1 = HIGH VID = VIN_ _ - VIN_ _ tSWITCH VOD = 0V INB1 VOD = 0V INB0 1.5V VIL
Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram
OUT_ _ MAX9394/MAX9395 IN_ _ IN_ _ RL/2 PULSE GENERATOR 50 EN_ _ CL RL = 100 1% OUT_ _ CL = 1.0pF +1.25V CL RL/2
VEN_ _
1.5V
1.5V
3V 0V
tPHD VOUT_ _ WHEN VID = +100mV VOUT_ _ WHEN VID = -100mV 50%
tPDH 50%
VOUT_ _ WHEN VID = -100mV VOUT_ _ WHEN VID = +100mV tPHD
50% tPDH VID = VIN_ _ - VIN_ _
50%
Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram 8 _______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
Table 1. Input Select Truth Table
LOGIC INPUTS LB_SELA 0 0 0 1 1 1 1 X = Don't care. LB_SELB 0 0 1 0 0 1 1 BSEL 0 1 X 0 1 0 1 DIFFERENTIAL OUTPUTS OUTA_ / OUTA_ INA selected INA selected INA selected INB0 selected INB1 selected INB0 selected INB1 selected OUTB / OUTB INB0 selected INB1 selected INA selected INB0 selected INB1 selected INA selected INA selected
LB_SELA
INA PULSE GENERATOR INA 0
MAX9394 MAX9395
CL OUTA0 RL
50
50
LB
CL
OUTA0
FROM CHANNEL B
CL OUTA1 RL CL OUTA1 RL = 100 1% CL = 1.0pF
ENA0 = ENA1 = HIGH 1 CHANNEL SHOWN.
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects.
Table 2. Loopback Select Truth Table
LB_SEL_ GND or open VCC OUT_ _ Normal inputs selected. Loopback inputs selected.
Board Layout
Use a four-layer printed circuit (PC) board providing separate signal, power, and ground planes for highspeed signaling applications. Bypass VCC to GND as close to the device as possible. Install termination resistors as close to receiver inputs as possible. Match the electrical length of the differential traces to minimize signal skew.
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9
2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
VOUTA0 VOD = 0V VOUTA0 tCCS VOUTA1 VOD = 0V VOUTA1 VOD = VOUT_ _ - VOUT_ _ VOD = 0V tCCS VOD = 0V
Figure 6. Output Channel-to-Channel Skew
Functional Diagram
LB_SELA ENA0
MAX9394 MAX9395
OUTA0 OUTA0 0
INA INA
LB
OUTA1 OUTA1
LB_SELB LB 0
ENA1 INB0
OUTB OUTB ENB
INB0
0 INB1 1 INB1 BSEL
10
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2:1 Multiplexers and 1:2 Demultiplexers with Loopback
Pin Configurations
MAX9394/MAX9395
LB_SELA
TOP VIEW
N.C. N.C. N.C. VCC
GND
INA
INA
TOP VIEW
N.C. VCC 28 27
LB_SELA
GND 23
32 N.C. 1 N.C. 2 N.C. 3 GND 4 ENB 5 OUTB 6 OUTB 7 VCC 8 9 GND
31
30
29
28
27
26
25 24 VCC 23 OUTA0 22 OUTA0 21 ENA0
26
25
24
N.C. 1 N.C. 2 GND 3 ENB 4 OUTB 5 OUTB 6 VCC 7 8 GND 9 INB0 10 INB0 11 LB_SELB 12 INB1 13 INB1 14 BSEL MAX9394 MAX9395 *EXPOSED PADDLE
VCC 22 21 OUTA0 20 OUTA0 19 ENA0 18 GND 17 OUTA1 16 OUTA1 15 ENA1
INA
MAX9394 MAX9395
20 GND 19 OUTA1 18 OUTA1 17 ENA1
10 INB0
11 INB0
12 LB_SELB
13 VCC
14 INB1
15 INB1
16 BSEL
THIN QFN
*CONNECT EXPOSED PADDLE TO GND.
TQFP
Chip Information
TRANSISTOR COUNT: 1565 PROCESS: Bipolar
______________________________________________________________________________________
INA
11
2:1 Multiplexers and 1:2 Demultiplexers with Loopback MAX9394/MAX9395
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
REV.
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
12
______________________________________________________________________________________
2:1 Multiplexers and 1:2 Demultiplexers with Loopback
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L TQFP, 5x5x01.0.EPS
MAX9394/MAX9395
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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